From 51a8ce4dade0c8f953bde3224b7a1b978175b7d8 Mon Sep 17 00:00:00 2001 From: Willy Tarreau Date: Sun, 30 Dec 2018 16:32:15 +0100 Subject: drivers/clk: add a few intermediary operating points for rockchip RK3399 Some little cores can't support 1800 MHz, let's try 1752. --- drivers/clk/rockchip/clk-rk3399.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 53376df..fda19d1 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -444,7 +444,9 @@ static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), + RK3399_CPUCLKL_RATE(1752000000, 1, 8, 8), RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), + RK3399_CPUCLKL_RATE(1656000000, 1, 7, 7), RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), @@ -463,7 +465,9 @@ static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), + RK3399_CPUCLKB_RATE(2112000000, 1, 11, 11), RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), + RK3399_CPUCLKB_RATE(2064000000, 1, 10, 10), RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9), RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), -- 2.9.0